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This field records the Chief Examiner for unit approval purposes. It does not publish, and can only be edited by Faculty Office staff
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NB: This view restricted to entries modified on or after 19990401000000
The unit codes CSC1082 (in 1998) and then CSE1308 were alias codes for the first year BDigSys core unit "Digital Technology I" ( DGS1111/CSE1101) but with the unit re-badged as "Digital Logic". This was then promoted as an elective unit at first year level in the BcompSci, and later in the BSoftEng. The renaming / recoding was not technically necessary but reflects the politics of department amalgamations at the time.
The unit gives an introduction to digital logic design, and was the first in the 5 unit BdigSys digital core sequence of: Digital Technology 1, Digital Technology 2, Digital Design 1, Digital Design 2, and Digital Design 3. As a BCompSci or BSoftEng elective its value is to introduce computer hardware basics and provide a bridge to later units in Computer Architecture and Computer Organisation.
At the completion of the subject, the students should understand the operation and behaviour of the various logic gates which are the building blocks of digital logic circuits and be familiar with various number systems and representations common in the digital design and computing areas. They should have competence in the design and minimisation methods of combinational logic circuits of up to six input variables and be familiar with the combinational logic building blocks like decoders, multiplexers and the use of ROMs and other programmable logic devices (PLDs) to solve combinational logic problems. They should have a working knowledge of the laws of two-state Boolean Algebra, and be able to transform logic expressions into various standard forms. On the sequential logic front they should have knowledge of latches and flip-flops and be able to both design and analyse sequential circuits with a dozen or so states, inputs and outputs. They should be familiar with the state equation, the state table, and the state diagram representations of these circuits. They should be familiar with counters, registers, state machines and other manifestations of sequential logic circuits. On the practical side they should develop abilities in implementing circuits by wiring together commercially available integrated circuits. They will have an understanding of some real-world device behaviours not apparent in the simplified "blackboard world". They should have developed some skills in fault finding by constructing then testing a reasonable sequence of fault hypotheses.
An objective here is to develop the belief that complex logic circuits can usually be partitioned into a number of smaller and understandable blocks. The "divide and conquer" approach can be applied outside of circuit analysis.
The practical programme of the unit involves both the uses of CAD logic design and simulation tools and the building of real circuits on prototype wiring boards. The first builds skills in the fast entry of design information into a CAD system. The second hones motor skills necessary for the fine placement of connecting wires and the planning and layout skills necessary for constructing complex systems requiring >100 connections.
The best I hope for here is to practice communicating technical ideas and information to others in an accurate and unambiguous way.
The unit is an introductory course in digital logic design and includes the necessary background on binary and other numbering systems plus various number representation formats useful in digital design and general computing.
Students learn combinational logic design methods and minimisation techniques. This includes: truth tables, standard forms, Karnaugh maps, Boolean algebra, Decoders, muxes, adders, ROMs and PLDs. They learn how signal feedback creates latches and flip-flops which exhibit memory effects. Sequential logic design and analysis topics count for about half of the unit. These include: counter, register and state machine design and the state equation, state table, and state diagram representations.
The unit has a large laboratory component including design and implementation exercises using both CAD design and simulation tools, as well as prototype wiring boards with commercial integrated circuit components.
"Digital Design" by Morris M Mano, second edition 1991 (Prentice-Hall).
On-campus
Lectures
Tutorials
Practicals
Assignments(2)
Unit tests(3)
Lectures: C1,C2,C3,C4
Tutorials: C1,C2,C3,C4,C5,A1,A2
Practicals: C1-C5,P1-P5
Assignments: C4,C5,C6,P7
Writen examination (3 hours): 55%
Examination and tests: C1 to C5
Practical work: P1 to P5
Tutorial work: C1 to C5, S1 to S3
Assignments: C1 to C6, P6 and P7
6
Approx 120 - 150 hours total commitment for the semester.
Lectures: 26 hrs, Practicals: 36hrs, Tutes & tests: 12hrs, Prac prep/write up: 15 hrs, Assignments: 10hrs, Self-directed study: 20-50hrs
Hi-Tech: 1 x 1hr/week, Low-Tech:(blackboards): 1 x 1hr/week
Small Low-Tech lecture theatre with blackboards: 4 x 1hr/week
Spacious computer lab needed, (eg Rm 138/63) with storage cupboards for extra equipment such as 5V power supplies and "DLT" interface boards. Computers to run Windows OS with network access. Machines need 25-pin printer port to allow the "Digital Logic Trainer" interface board to be connected.
Approx 1.5 EAS including lab demonstrators.
Digital Logic Training package "DLT.exe" (authored by P. Atkinson) served to Windows lab machines from Novell fileserver. Note under windows XP the I/O permissions bit map needs to be modified to allow user level 3 code direct access to the ports controlling the parallel printer port. Administrator level access to the lab machines is needed for this modification.
100% Computer Science and Software Engineering (or sucessor)
None
None
Approx 100Mb of space on an ITS filesever that can be managed by the unit coordinator to serve unit materials and recieve electronic design files submitted by students.
None.
CFR1130, COT1130, GCO2812, ECE2701 and the variously coded reincarnations of itself: RDT1111, DGS1111, CSC1082, CSC2061, CSE1011, CSE2306
CSE2306 (and CSE1101, not offered from 2005 on)
1 (student's perception ~1.5)
The unit has no research training component.
First appearance as CSE1308 code was in 1999, but similar content has been delivered under various other codes since about 1993.
S1
From 1998 to 2003 it varied beteen 130 - 170 (including all alias code enrolments). In 2004 with no BDigSys intake the enrolment was approx 85 students.
Clayton. (also in Malaysia 1999 to 2003)
07 Dec 2004 | Peter Atkinson | Updated avatar entry from the original skeleton created by jah. No significant changes since that time but update needed for an (over)due unit review. |
17 Oct 2005 | David Sole | Added Software requrirements template |
21 Oct 2005 | David Sole | Updated requirements template to new format |
12 Dec 2007 | Julianna Dawidowicz | modified UnitName |
12 Dec 2007 | Julianna Dawidowicz | CSE1308 Chief Examiner Approval, ( proxy school approval ) |
12 Dec 2007 | Julianna Dawidowicz | FEC Approval |
12 Dec 2007 | Julianna Dawidowicz | FacultyBoard Approval - Faculty Board approved the disestablishment of this unit at 05/07 meeting |
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