Successfully completing students should comprehend the following aspects of a small microprocessor system:

Objective here is to replace the "magic box" perception of microprocessors with something akin to "a box of understandable components with clever interconnection and orchestration"..

To become a proficient user of typical software development/simulator tools for assembly language programs.

The unit content is a detailed study of the operation and low-level programming of a representative 8-bit microprocessor "from the inside out". Approximately equal amounts of time are devoted to the hardware aspects of how the CPU functions both internally and externally, and to the software aspects of how programs are designed , written and tested for such systems.

An unusual aspect of the unit is the use of purpose built logic simulation tools which allow student experimentation at the hardware/architecture level. Students can write micro-code for the CPU's control store to define how a machine instruction works (or doesn't!). They might extend the architecture by adding new CPU registers and then develop new micro-code, for a new instruction that uses their new register. Similarly outside the CPU they design I/O ports and attach them to the processor buses and check for correct operation (and hence check that their understanding of bus signals and address decoding is correct).

"The 6800 Microprocessor" by Jack Quin, Macmillian Publishing 1992.

On-campus

Lectures

Tutorials

Practicals

Assignments(2)

Unit tests(3)

Lectures: C1,C2,C3,C4

Tutorials: C1,C2,C3,C4,C5,A1,A2

Practicals: C1-C5,P1-P5

Assignments: C4,C5,C6,P7

Examination and tests: C1 to C5

Practical work: P1 to P5

Tutorial work: C1 to C5, S1 to S3

Assignments: C1 to C6, P6 and P7

6

Approx 120 - 150 hours total commitment for the semester.

Lectures: 26 hrs, Practicals: 36hrs, Tutes:12hrs, Prac prep/write up: 15hrs, Self-directed study: 30-60hrs

Hi-Tech: 1 x 1hr/week, Low-Tech(blackboards): 1 x 1hr/week

Small Low-Tech lecture theatre with blackboards: 4 x 1hr/week

Spacious computer lab (eg Rm 138/63) with windows PCs and network access.

Approx 1.0 EAS

• Software Title:
• Vendor:
• Version:
• OS: MS Windows XP ( ) and/or LINUX ( )
• License Details: (A valid software license certificate/s or Vendor permission must be available upon request if the software is to be installed for teaching)
• Are we currently licensed: Yes ( ) or No ( ) (If unsure, please check with your local IT support )
• If (Yes), who is the contact person for this software?:
• If (No), will the software license be arranged by: Staff member requesting the software ( ) or Technical Services* ( ) ? *If the latter is selected, please discuss your requirement/s with myself ASAP, prior to finalising your request, as there could be financial or resourcing implications.
• Is the software to be installed and accessed from a: Client/Workstation ( ), or Server ( ) ?
• Type of license: Site License ( ), Freeware ( ), FOSS (Free and Open Source Software) ( ), Shareware ( ), Lab based ( ) # of Licenses needed ____
• In what week will you commence using the software in class? Semester 1 (Week ___ ) and/or Semester 2 (Week ___ ):
• Nominated Staff For Acceptance Testing Software: (Name) (Phone) (Email)
• Additional Information: Special Requirements, Software Configuration/Installation Requirements, etc:

Assembly language development package:"dev6801.exe" and Digital Logic Training package:"DLT.exe". Both packages written in-house (P. Atkinson) and served to Windows lab machines from Novell fileserver.

100% CSSE

None.

None.

RDT1111 or DGS1111 or CSE1101 or CSE1308 or CSE2306

Competence in binary and hexadecimal numbering. Knowledge of behaviour of: AND, NAND, OR, NOR, XOR, XNOR, NOT logic gates and competence in combinational logic design and minimisation techniques. Knowledge of : Decoders, Multiplexers, ROMS, Latches, Flip-flops, Counters, Registers, State machines and competence in sequential logic design methods. Some prior experience with the "DLT" logic designer/simulator software is preferred.